Large digital and/or mixed-signal integrated circuits (IC) often contain multiple power supply domains. A power supply domain is a block of circuitry that receives the operating power from a unique source of power supply. For example, a mixed-signal chip may use one power supply for the (usually larger) digital section, and a second for the (usually smaller) analog section. This arrangement keeps digital switching noise arising in the digital section from interfering with potentially noise-sensitive analog signals in the analog section. Complexity of cross-domain signaling interface circuits increases as a large number of low voltage precision signal processing circuits are integrated in the same system (or, system on a chip (SoC)) along with the large digital control circuitry, microelectromechanical (MEMS) sensors, and high voltage power drivers. While this array of different voltage domains enables ambitious applications to be monolithically integrated into the same substrate, it poses challenges to the robustness of the circuit during cross domain powering and cross-domains stress events.
FIG. 1 illustrates a layout of a mixed-signal integrated circuit (IC) 2 that includes multiple power supply domains. The mixed-signal IC as shown in FIG. 1 includes an analog circuit section 4, a digital circuit section 6, and an input/output (I/O) circuit section 8. Each of these circuit sections is coupled to a unique power supply. Commonly, the negative terminals of all the supply domains are connected together on the circuit board, though they may or may not be connected together on the chip. The positive terminals may be at the same or different voltages. Referring to FIG. 1, the positive terminal of the digital domain is labeled as DVDD and negative terminal is labeled as DVSS. Similarly, the positive and negative terminals of the analog section and the I/O section may be labeled as AVDD/AVSS and IOVDD/IOVSS, respectively. We will further assume that all _VSS terminals are intended to be at essentially the same electrical potential, this being accomplished by direct connection either on- or off-chip.
The circuit sections may be interconnected via cross-domain signal links. For example, the analog circuit section 4 is connected to the digital circuit section 6 via a cross-domain signal link 10 and connected to the I/O circuit section 8 via a cross-domain signal link 14. Digital circuit section 6 is connected to I/O circuit section 8 via a cross-domain signal link 12. In many cases, all supply domains are powered by the IC user's system. There is no a priori guarantee that power is applied to all domains simultaneously, nor is there any specified limit on the amount of time that might elapse between application of power to the first domain and application of power to the second (or third, or fourth).
It is often desirable to ensure that digital control signals crossing from one domain to another are in well-defined states before all domains are powered. This is especially true when a receiving domain is powered, but the associated transmitting domain is not. It is possible that the receiving circuit could dissipate large amounts of power if the driving signal is not well-defined, causing localized heating or unnecessarily draining a battery. If dedicated cross-domain electrostatic (ESD) protection devices are situated between domains to enhance the IC robustness, those devices can actually be overstressed and get damaged, since they are not designed to operate in DC conditions.
To overcome these problems, level-translators are often employed to interface cross-domain signals (even if the two domains operate at the same nominal supply voltage). Level-translators that provide a deterministic output value if one of the domain supplies is absent are known in the art. Thus, a level-translator is used for each interconnection between two circuit sections. However, when a large number of circuit sections co-exist on a mixed-signal IC, the number of level translators needed is proportionally large and can consume a substantial amount of die area with increased cost. Further, level-translators interpose an additional delay in signal transmission that may be unacceptable for signals with critical timing requirements. Finally, level translators remain active at all times, thereby increasing power dissipation when the cross-domain signals are actively switching.